Automatic Generation of Assertions for Formal Veri cation of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation

For verifying complex sequential blocks such as microprocessor embedded arrays, the formal method of symbolic trajectory evaluation (STE) has achieved great success in the past [[3], [5], [6]]. Past STE methodology for arrays requires manual creation of \assertions" to which both the RTL view and the actual design should be equivalent. In this paper, we describe a novel method to automate the assertion creation process which improves the e ciency and the quality of array veri cation. Encouraging results on recent PowerPC arrays will be presented.